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3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module 168 pin unbuffered DIMM Modules
HYS64V8000GU-10 HYS72V8000GU-10
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168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications 1 bank 8M x 64, 8M x 72 organisation Optimized for byte-write non-parity or ECC applications Fully PC66 layout compatible JEDEC standard Synchronous DRAMs (SDRAM) Performance:
-10 fCK tAC Max. Clock frequency Max. access time from clock 66 MHz @ CL=2 100 MHz @ CL=3 8 ns @ CL=2 7 ns @ CL=3
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Single +3.3V( 0.3V ) power supply Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh Decoupling capacitors mounted on substrate All inputs, outputs are LVTTL compatible Serial Presence Detect with E 2PROM Utilizes eight / nine 8M x 8 SDRAMs in TSOPII-54 packages 4096 refresh cycles every 64 ms Gold contact pad Card Size: 133,35mm x 25,40mm x 4,00 mm
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Semiconductor Group
1
2.98
HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module
The HYS64(72)V8000GU-10 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organised as 8M x 64 and 8M x 72 high speed memory arrays designed with Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use eight 8M x 8 SDRAMs for the 8M x 64 organisation and an additional SDRAM for the 8M x 72 organisation. Decoupling capacitors are mounted on the PC board. The DIMMs have a serial presence detect, implemented with a serial E 2PROM using the two pin I 2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint. Ordering Information
Type HYS 64V8000GU-10 HYS 72V8000GU-10 Ordering Code Package L-DIM-168-23 L-DIM-168-23 Descriptions PC66 8M x 64 SDRAM module PC66 8M x 72 SDRAM module
Pin Names
A0-A11 BA0,BA1 DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0 CLK0, CLK1 DQMB0 - DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C. Address Inputs( RA0 ~ RA11 / CA0 ~ CA8) Bank Selects Data Input/Output Check Bits (x72 organisation only) Row Address Strobe Column Address Strobe Read / Write Input Clock Enable Clock Input Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect No Connection
Address Format:
8M x 64 8M x 72 Part Number HYS 64V8000GU HYS 72V8000GU Rows 12 12 Columns 9 9 Bank Select 2 2 Refresh 4k 4k Period 64 ms 64 ms Interval 15,6 s 15,6 s
Semiconductor Group
2
HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module
Pin Configuration
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC (CB0) NC (CB1) VSS NC NC VCC WE DQMB0 DQMB1 CS0 DU VSS A0 A2 A4 A6 A8 A10 BA1 VCC VCC CLK0 PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol VSS DU CS2 DQMB2 DQMB3 DU VCC NC NC NC (CB2) NC (CB3) VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC DU NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC SDA SCL VCC PIN # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Symbol VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC (CB4) NC (CB5) VSS NC NC VCC CAS DQMB4 DQMB5 NC RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 NC PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS CKE0 NC DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VCC
Note : Pinnames in brackets are for the x72 ECC versions
Semiconductor Group
3
HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module
WE CS0 DQMB0 DQ0-DQ7 CS WE DQM DQ0-DQ7 D0 CS WE DQMB1 DQ8-DQ15 DQM DQ0-DQ7 D1 CS WE DQM CB0-CB7 CS2 DQMB2 DQ16-DQ23 CS WE DQM DQ0-DQ7 D2 CS WE DQMB3 DQ24-DQ31 DQM DQ0-DQ7 D3 D0 - D7,(D8) D0 - D7,(D8) C0-C15,(C16,C17) D0 - D7,(D8) D0 - D7,(D8) D0 - D7,(D8) D0 - D7,(D8) CLK0 CLK1 CLK2,CLK3
R3 R4
CS WE DQMB4 DQ32-DQ39 DQM DQ0-DQ7 D4 CS WE DQMB5 DQ40-DQ47 DQM DQ0-DQ7 D5
DQ0-DQ7 D8
CS WE DQMB6 DQ48-DQ55 DQM DQ0-DQ7 D6 CS WE DQMB7 DQ56-DQ63 DQM DQ0-DQ7 D7 E2PROM (256wordx8bit) SA0 SA1 SA2 SA0 SA1 SA2
A0-A11,BA0,BA1 VCC VSS RAS CAS CKE0
Note:
SCL SDA
2 SDRAM 2 SDRAM 2 or 3 SDRAM 2 SDRAM
10 pF
1. D8 is only used in the x72 ECC version 2. All resistor values are 10 Ohms,except R3,R4=4,7 Ohm for the x72 version
Block Diagram for 8M x 64/72 SDRAM DIMM modules
Semiconductor Group
4
HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VDD,VDDQ = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 2.0 mA) Output low voltage (IOUT = 2.0 mA) Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VCC) Symbol Limit Values min. max. Vcc+0.3 0.8 - 0.4 40 40 V V V V A A 2.0 - 0.5 2.4 - - 40 - 40 Unit
VIH VIL VOH VOL II(L) IO(L)
Capacitance TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz Parameter Symbol Limit Values min. (x64) Input capacitance
(A0 to A11, BS0, BS1 RAS, CAS, WE)
Unit
max. (x72) 55 25 38 13 12 8 10 pF pF pF pF pF pF pF
CI1 CI2 CI3 CI4 CIO
Csc Csd
45 20 38 13 12 8 10
Input capacitance ( CS0 - CS3) Input capacitance (CLK0 - CLK3) Input capacitance (DQMB0 - DQMB7) Input / Output capacitance (DQ0-DQ63,CB0-CB7) Input Capacitance (SCL,SA0-2) Input/Output Capacitance
Semiconductor Group
5
HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module
Operating Currents (TA = 0 to 70 oC, VCC = 3.3V 0.3V
(Recommended Operating Conditions unless otherwise noted)
Parameter & Test Condition
OPERATING CURRENT trc=trcmin., tck=tckmin. Active-precharge command cycling, without burst operation PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) NO OPERATING CURRENT tck = min., CS = VIH(min), active state ( max. 4 banks) BURST OPERATING CURRENT tck = min., Read/Write command cycling AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V CKE>=VIh(min.) CKE<=VIl(max.) (Power down mode) tck = min. tck = Infinity tck = min. tck = Infinity 1 bank operation
Symb.
x64 max. 880
x72 990 mA
Note
ICC1
7
ICC2P ICC2PS ICC2 ICC2S
24 16 400 40 560 64 1240
27 18 450 45 630 72 1395
mA mA mA mA mA mA mA
7
7
ICC3 ICC3P ICC4
7,8
ICC5
1040
1170
mA
7
ICC6
16
18
mA
Notes:
7. These parameters depend on the cycle rate and these values are measured by the cycle rate under the .......minimum value of tck and trc. Input signals are changed one time during tck. 8. These parameter depend on output loading. Specified values are obtained with output open.
Semiconductor Group
6
HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module
AC Characteristics 1)2)3) TA = 0 to 70 C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 1 ns Parameter
Symbol
Limit Values -10
min max
Unit
Clock and Clock Enable
Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 Clock Frequency CAS Latency = 3 tCK CAS Latency = 2 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition time - - - - 3 3 0.5 100 66 7 8 - - 10 MHz MHz ns ns ns ns ns
4
10 15
- -
ns ns
tCH tCL tT
Setup and Hold Times
Command Setup Time Address Setup Time Data In Setup Time CKE Setup Time Command Hold Time Address Hold Time Data In Hold Time CKE Hold Time
tCS tAS tDS tCKS tCH tAH tDH tCKH
2.5 2.5 2.5 2.5 1 1 1 1
- - - - - - - -
ns ns ns ns ns ns ns ns
5 5 5 5 5 5 5 5
Common Parameters
Row to Column Delay Time Row Active Time Row Cycle Time Row Precharge Time
tRCD tRAS tRC tRP
30 60 90 30
-
100k
ns ns ns ns
6 6 6 6
- -
Semiconductor Group
7
HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module
Parameter
Symbol
Limit Values -10
min max
Unit
Activate(a) to Activate(b) Command period CAS(a) to CAS(b) Command period Mode Register Set-up time Power Down Mode Entry Time
tRRD tCCD tRSC tSB
20 1 20 0
- - - 10
ns CLK ns ns
6
Refresh Cycle
Refresh Period (4096 cycles) Self Refresh Exit Time
tREF tSREX
- 10
64
ms
Read Cycle
Data Out Hold Time
Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency
tOH tLZ tHZ tDQZ
3 0 3 2
- - 10 -
ns ns ns CLK
8
Write Cycle
Write Recovery Time CAS Latency = 3 tWR CAS Latency = 2 DQM Write Mask Latency 10 15 0 - - - ns ns CLK
tDQW
Semiconductor Group
8
HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module
Notes: 1. The specified values are valid when addresses are changed no more than once during tck(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). 2. The specified values are valid when data inputs (DQ' are stable during tRC(min.). s) 3. An initial pause of 100s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V il = 0.4 V and V ih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V ih and Vil. All AC measurements assume t T=1ns with the AC output load circuit shown.
tCH 2.4 V CLOCK 0.4 V tCL tSETUP tHOLD
tT
+ 1.4 V 50 Ohm
INPUT
1.4V
Z=50 Ohm I/O
tAC tLZ tOH tAC
50 pF
OUTPUT
1.4V
tHZ
fig.1
5. If clock rising time is longer than 1 ns, a time (t T/2 -0.5) ns has to be added to this parameter. 6. If tT is longer than 1 ns, a time (t T -1) ns has to be added to this parameter. 7. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to " ake-up"the device. w 8. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 9. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
Semiconductor Group
9
HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module
A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence detect protocol ( I 2C synchronous 2-wire bus) SPD-Table:
Byte# Description SPD Entry Value Hex x64 -10 80 08 04 0C 09 01 40 00 01 A0 70 00 80 08 00 01 8F 04 06 01 01 00 06 F0 80 FF FF 1E 14 x72 -10 80 08 04 0C 09 01 48 00 01 A0 70 02 80 08 08 01 8F 04 06 01 01 00 06 F0 80 FF FF 1E 14
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x 8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont' d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of internal SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General SDRAM Cycle Time at CL = 2 SDRAM Acces TIme from Clock at CL=2 SDRAM Cycle Time at CL = 1 SDRAM Acces TIme from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD
128 256 SDRAM 12 9 1 64 / 72 0 LVTTL 10 ns 7.0 ns none / ECC Self-Refresh, 15.6s x8 n/a / x8 tccd = 1 CLK 1, 2, 4, 8 & full page 4 CAS latencies = 2,3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 15 ns 8.0 ns not supported not supported 30 ns 20 ns
Semiconductor Group
10
HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module
SPD-Table ( cont' d)
Byte# Description SPD Entry Value Hex x64 x72 -10 -10 1E 1E 2D 2D 10 10 FF FF 12 7A FF FF 12 8C FF FF
29 30 31 32-61
Minimum RAS to CAS delay tRCD Minimum RAS pulse width tRAS Module Bank Density (per bank) Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufactures' information (optional) s 127 (FFh if not used) 128+ Unused storage locations
30 ns 45 ns 64 MByte
Revision 1.2a
L-DIM-168-23 SDRAM DIMM Module package
133,35 127,35 3,0
*)
3,0
1
10 11 42,18 66,68
40
41
84
85
94 95 A
124 B
125 C
168
+) CB's on x72 only
6,35 3,125 3,125
6,35 1,27 2,54 min. 1,0 + 0.5 -
2,0 Detail A Detail B
2,0
Detail C
DM168-23.WMF 8M x 64/72 SDRAM
preliminary drawing
Semiconductor Group
11
17,78
0,2 + 0,15 -
25,40

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